OKA is a translator of a processor pipeline hazards description (PHD) into code for fast recognition of pipeline hazards. Instruction execution can be started only if its issue conditions are satisfied. If not, instruction is interlocked until its conditions are satisfied. Such an "interlock (pipeline) delay" causes interruption of the fetching of successor instructions (or demands NOP instructions, e.g. for MIPS).
There are two major kind of interlock delays in modern superscalar RISC processors. The first one is data dependence delay. The instruction execution is not started until all source data has been evaluated by previous instructions (there are more complex cases when the instruction execution starts even when the data are not evaluated but will be ready till given time after the instruction execution start). Taking into account of such kind delay is simple. Data dependence (true, output, and anti-dependence) delay between two instructions is given by constant. In the most cases this approach is adequate. The second kind of interlock delay is reservation delay. Two such way dependent instructions under execution will be in need of shared processors resources, i.e. buses, internal registers, and/or functional units, which are reserved for some time. Taking into account of this kind of delay is complex especially for modern RISC processors. The goal of OKA is to generate code for fast recognition of such kind delay (pipeline hazards).